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Papayaved
ID 747968374
Type user
Username @papayaved
First Name Papayaved
First Seen 2026-01-11 09:43 UTC
Updated 2026-01-11 09:43 UTC
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CY iT HR
@cyprusithr 		1 2023-08-12 17:54 UTC 2023-08-12 17:54 UTC
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CY iT HR 2023-08-12 17:54 UTC document
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#CV FPGA design engineer, microcontroller programmer.

RTL design: Verilog, SystemVerilog, VHDL, Altera, Xilinx, GoWin, Quatrus, Vivado, ModelSim, QuestaSim.

Embedded: C, RTOS, STM32, XMOS, NIOS, AVR, ESP32, Raspberry Pi.

Desktop apps: C++, C#, MatLab, Python, Qt, Visual Studio.

Electronics design: schematic, PCB, PCBA, Altium Design, EasyEDA.

Additional: digital signal processign (FIR, CIC, Hilbert, FFT, PSK modulation), G-code, CNC machines, PLC, radar systems, ultrasonic, substations (GOOSE/GSE), PCI, Ethernet, SerDes LVDS, CAN, CanOpen, ModBus, SQL, HTML, JavaScript