Channels / CY iT HR
CY iT HR
@cyprusithr · supergroup
· filtered by
Papayaved
📄 Document (not supported)
#CV FPGA design engineer, microcontroller programmer.
RTL design: Verilog, SystemVerilog, VHDL, Altera, Xilinx, GoWin, Quatrus, Vivado, ModelSim, QuestaSim.
Embedded: C, RTOS, STM32, XMOS, NIOS, AVR, ESP32, Raspberry Pi.
Desktop apps: C++, C#, MatLab, Python, Qt, Visual Studio.
Electronics design: schematic, PCB, PCBA, Altium Design, EasyEDA.
Additional: digital signal processign (FIR, CIC, Hilbert, FFT, PSK modulation), G-code, CNC machines, PLC, radar systems, ultrasonic, substations (GOOSE/GSE), PCI, Ethernet, SerDes LVDS, CAN, CanOpen, ModBus, SQL, HTML, JavaScript
RTL design: Verilog, SystemVerilog, VHDL, Altera, Xilinx, GoWin, Quatrus, Vivado, ModelSim, QuestaSim.
Embedded: C, RTOS, STM32, XMOS, NIOS, AVR, ESP32, Raspberry Pi.
Desktop apps: C++, C#, MatLab, Python, Qt, Visual Studio.
Electronics design: schematic, PCB, PCBA, Altium Design, EasyEDA.
Additional: digital signal processign (FIR, CIC, Hilbert, FFT, PSK modulation), G-code, CNC machines, PLC, radar systems, ultrasonic, substations (GOOSE/GSE), PCI, Ethernet, SerDes LVDS, CAN, CanOpen, ModBus, SQL, HTML, JavaScript